From 24c0c25207a112d3a43f8c839e9f3d8608412d4d Mon Sep 17 00:00:00 2001
From: Xiao Wang <jasowang@redhat.com>
Date: Fri, 10 Aug 2012 09:03:43 -0300
Subject: [RHEL6 qemu-kvm PATCH 3/9] e1000: introduce bits of PHY control
 register

RH-Author: Xiao Wang <jasowang@redhat.com>
Message-id: <1344589429-3229-4-git-send-email-jasowang@redhat.com>
Patchwork-id: 40677
O-Subject: [RHEL6.4 qemu-kvm 3/9] e1000: introduce bits of PHY control register
Bugzilla: 607510 819915
RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
RH-Acked-by: Alex Williamson <alex.williamson@redhat.com>
RH-Acked-by: Vlad Yasevich <vyasevic@redhat.com>

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=607510

This would be used be following patches.

Signed-off-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
(cherry picked from commit 2e54cc21ad60219229df569a857a453285795565)
---
 hw/e1000_hw.h |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 hw/e1000_hw.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/hw/e1000_hw.h b/hw/e1000_hw.h
index 2e341ac..68a5415 100644
--- a/hw/e1000_hw.h
+++ b/hw/e1000_hw.h
@@ -349,6 +349,18 @@
 #define M88E1000_PHY_VCO_REG_BIT8  0x100 /* Bits 8 & 11 are adjusted for */
 #define M88E1000_PHY_VCO_REG_BIT11 0x800    /* improved BER performance */
 
+/* PHY Control Register */
+#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
+#define MII_CR_FULL_DUPLEX      0x0100 /* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
+#define MII_CR_ISOLATE          0x0400 /* Isolate PHY from MII */
+#define MII_CR_POWER_DOWN       0x0800 /* Power down */
+#define MII_CR_AUTO_NEG_EN      0x1000 /* Auto Neg Enable */
+#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_LOOPBACK         0x4000 /* 0 = normal, 1 = loopback */
+#define MII_CR_RESET            0x8000 /* 0 = normal, 1 = PHY reset */
+
 /* PHY Status Register */
 #define MII_SR_EXTENDED_CAPS     0x0001	/* Extended register capabilities */
 #define MII_SR_JABBER_DETECT     0x0002	/* Jabber Detected */
-- 
1.7.11.2

